Modern digital systems typically include an address bus and a data bus for communicating digital values. In a common application, a memory controller is linked to multiple memory modules through a multi-drop address bus and a multi-drop data bus. Signals on the address bus denote the memory location being accessed by the controller. The signals on the data bus serve to transfer data to/from the addressed memory locations. FIG. 1 shows such a system.
The FIG. 1 system includes a memory controller 5, a first memory module 10, and a second memory module 15. The controller and memory modules are coupled together by a multi-drop address bus 20 and a multi-drop data bus 25. The address bus is made up of “N” address signal lines, and the data bus is made up of “M” data signal lines. Each of the buses is made up of two segments. The address bus is made up of segments 20a and 20b, and the data bus is made up of segments 25a and 25b. Segment 20a includes individual address bus line segments 20a1-20aN, and segment 20b includes individual address bus line segments 20b1-20bN. Similarly, segment 25a includes individual data bus line segments 25a1-25aM, and segment 25b includes individual data bus line segments 25b1-25bM. It is noted that “N” and “M” are integers greater than or equal to 1, and that “N” and “M” may be the same integer (e.g. 32) or different integers.
In order to maximize the rate at which the system of FIG. 1 operates, the rate at which digital signals are transmitted over the address and data lines must be maximized. That is, the maximum rate of system operation is dependant on the rate at which digital symbols appearing on the address and data lines can be distinguished from temporally adjacent symbols appearing on the same line. If one assumes an unlimited rate of sampling for signals appearing on the address and data lines, and perfectly synchronized sampling, then the limiting factor in distinguishing the symbols appearing on the lines is the rate at which digital states of the signals appearing on the lines can be unambiguously determined from one digital state to another. Accordingly, the maximum rate of system operation is dependant upon how fast the digital states of the address and data signals can be unambiguously determined in a binary system, the rate of system operation is dependant upon how fast the binary states of the address and data signals can be unambiguously determined.